The present invention relates to a method and apparatus for driving a solid state image sensor which operates an electronic shutter.
An image sensing apparatus which has a solid state image sensor, like a CCD (Charge Coupled Device), controls the exposure of the solid state image sensor to achieve an optimal exposure state. This exposure control uses an iris mechanism which mechanically controls the amount of incident light to the solid state image sensor in accordance with the luminance of light reflected from a target object. Alternatively, the exposure control can use a so-called electronic shutter which controls the period the solid state image sensor accumlates a charge in accordance with the luminance of light reflected from the target object. The solid state image sensor has light-receiving pixels arranged in a matrix form, which stores (accumlates) information charges that are generated in accordance with the incident light.
FIG. 1 is a block diagram showing the structure of a prior art solid state image sensor, and FIG. 2 is a timing chart showing the operation of the prior art solid state image sensor. Referring to FIG. 1, a frame transferring type CCD solid state image sensor 1 includes a light-receiving section 1i, a storing section 1s, a horizontal transferring section 1h, and an output section 1d. The light receiving section 1i has a plurality of parallel transfer registers arranged continuously in the vertical direction. A plurality of light-receiving pixels are formed by each bit of the transfer registers. When the light from a target object irradiates the light-receiving pixels, each light-receiving pixel generates and stores a charge corresponding to the image of the target object. The storing section is has a plurality of transfer registers continuing from the transfer registers of the light-receiving section 1i. The number of bits of each transfer register of the storing section is 1s the same as that of each transfer register (shift register) of the light-receiving portion 1i. The storing section is temporarily stores information charges corresponding to a single display image output by the light-receiving section 1i. The horizontal transfer section 1h has a single horizontal transfer register. Each bit of the horizontal transfer register is connected to the transfer registers of the storing section is. The horizontal transfer section 1h receives the stored information charges, which correspond to the display image, from the storing section is in units of single lines and sequentially transfers the single line units to the output section 1d. The output section 1d has an electrically independent capacitor and an amplifier, which eliminate potential changes at the output section 1d. The output section 1d receives the information charges serially from the horizontal transfer section 1h in single line units and converts the information charges to a voltage value and then outputs an image signal Y(t).
A clock generator 2 generates a multi-phase vertical transfer clock φv, a storage transfer clock φs, and a horizontal transfer clock φh in response to horizontal and vertical timing signals HT, VT. The vertical transfer clock φv is sent to the light-receiving section 1i of the solid state image sensor 1, the storage transfer clock φs is sent to the storage section 1s, and the horizontal transfer clock φh is sent to the horizontal transfer section 1h. 
When the light-receiving section 1i receives the vertical transfer clock φv, the stored information charges in each light-receiving pixel of the light-receiving section 1i are transferred to the storage section is. This is the vertical scanning return period. When the storage section is receives the storage transfer clock φs, the information charges transferred from the light-receiving section 1i in accordance with the vertical transfer clock φv are acquired by the storage section 1s. Additionally, the acquired information charges are transferred to the horizontal transfer section 1h one line at a time. The information charges transferred to the horizontal transfer section 1h one line at a time in accordance with the storage transfer clock φs are further transferred to the output section 1d, sequentially. The clock generator 2 also generates a substrate clock φb which rises for a predetermined time period in response to a discharge timing signal BT. The substrate clock φb is applied to the substrate side of the solid state image sensor 1. When the substrate clock φb is active, the information charges stored in the light-receiving pixels of the light-receiving section 1i are discharged toward the substrate side. Since the vertical transfer clock φv falls synchronously with the rising of the substrate clock φb, the discharge of information charges toward the substrate is smooth.
In this manner, information charges are stored in each light-receiving pixel of the light-receiving section 1i during a period L, which starts from when the discharge of information charges in accordance with the substrate clock φb is completed to when transmission is commenced by the vertical transfer clock φv. The stored period of the information charges, or the shutter speed, is controlled by adjusting the timing of the substrate clock φb.
A timing controller 3 generates the vertical timing signal VT and the horizontal timing signal HT from a reference clock CK, which has a constant cycle, and sends the signals VT, HT to the clock generator 2. If, for example, the NTSC standard is employed, the timing controller 3 causes the horizontal timing signal HT to rise each time 910 reference clocks CK, which frequency is 14.32 MHz, are counted. The timing controller 3 also causes the vertical timing signal VT to fall each time 525/2 horizontal timing signals HT are counted. The timing controller 3 also causes the discharge timing signal BT to rise during the vertical scanning period based on exposure data indicating the exposure level of the solid state image sensor 1. The timing controller 3, for example, determines whether or not the exposure data, which is obtained by integrating the image signal Y(t) for every single display image unit, is within an optimal range. If the exposure data exceeds the exposure range, the rising timing of the pulse signals is delayed to shorten the storage period L of the information charges. On the other hand, if the exposure data has not yet reached the optimal level, the timing controller 3 advances the rise timing of the pulse signals to prolong the storage period L of the information charges.
The image sensor maintains the image signal Y(t) at an optimal level by changing the length of the period L, during which information charges are stored in the light-receiving section 1i, in accordance with the level of the image signal Y(t).
FIG. 3 is a cross-sectional view showing the light-receiving section 1i of a CCD solid state image sensor which employs a vertical overflow drain structure to absorb excess information charges on the substrate side. A diffusion region (P-well region) 12 having a P type conductivity is formed on the surface region of a semiconductor substrate 11 which has an N type conductivity and where a drain region is to be formed. Formed on the surface of this P-well region 12 is a diffusion layer (buried layer) 13 which has an N type conductivity and where a channel region is to be formed. The buried layer 13 is formed so as to be defined by an isolation region (not shown) on the surface of the P-well region 12 and to extend in one direction. First gate electrodes 15 are arranged at given intervals on the buried layer 13 via an insulating layer 14, and second gate electrodes 16 are arranged between the adjoining first gate electrodes 15 in such a way as to partially cover the first gate electrodes 15. The first and second gate electrodes 15, 16 are respectively supplied with four phase vertical clocks φv (φv1–φv4), each of which has a phase difference of 90 degrees from one to another and are synchronous with a vertical sync signal VD. The semiconductor substrate 11 is supplied with the substrate clock φb. A ground voltage is applied to the P-well region 12. The peak values of the vertical clocks φv1–φv4 and the substrate clock φb, or the potentials at the gate electrodes 15, 16 and the semiconductor substrate 11, are set based on the P-Well region 12.
In the vertical overflow drain structure, when the light-receiving section 1i stores information charges, the substrate clock φb is kept low, and one to three of the vertical clocks (φv1–φv4) are kept high. This selectively activates the first and second gate electrodes 15, 16. In the part of the light-receiving section 1i where the first and second gate electrodes 15, 16 are activated, as shown in FIG. 4, a potential well (depletion layer) is formed near the buried layer 13. Accordingly, information charges are stored in the region from within the buried layer 13 to the surface of the P-well region 12. In the part of the light-receiving section 1i where the first and second gate electrodes 15, 16 are deactivated, a potential well is not formed in the buried layer 13 but a potential barrier for defining the light-receiving pixels is formed in the buried layer 13.
During the shutter operation for discharging the information charges stored in each of the light-receiving pixels, all of the vertical clocks φv1–φv4 are kept low and the substrate clock φb rises. Consequently, the potential well in the buried layer 13 becomes shallower while the potential well in the semiconductor substrate 11 becomes deeper. As a result, the potential barrier in the P-well region 12 disappears as indicated by the broken line in FIG. 4. In this manner, the information charges stored in the potential well in the buried layer 13 are moved to the semiconductor substrate 11 from the buried layer 13 along the potential profile and are discharged therefrom.
In the solid state image sensor 1 having the vertical overflow drain structure, the output section 1d and the light receiving section 1i are formed on the same substrate. Thus, the substrate clock φb affects the output portion 1d during the shutter operation. Accordingly, the rise timing of the substrate clock φb is set within the horizontal scanning return period in order to prevent noise from being mixed with the image signal Y(t) acquired from the output portion 1d. However, the horizontal scanning return period is very short, lasting only a few microseconds. Hence, if charges are stored in a large number of light-receiving pixels, all of the unnecessary charges in the light-receiving pixels may not be discharged and may thus remain in the light receiving pixels as residual charges. The residual charges may mix with the subsequently stored information charges and decrease the quality of the replayed display image.